The increasing application of integrated circuits, and particularly FET devices has necessarily resulted in striking compromises between antithetical considerations. Of prime importance is the optimization of logic circuit density and speed, and typically optimizing device geometry based on these criteria necessarily require sacrifices to be made in respect of other parameters, one particular parameter being breakdown voltage. However, some applications are now being uncovered in which the reduced breakdown voltage of FET devices has proved an impediment. One typical example is electrically alterable read only storage (EAROS). It has been found that to program and erase the storage array it is necessary to selectively route high voltages to particular nodes in the array. The relative term "high" should be taken in the context of all FET devices, particularly devices optimized for increased density and speed. For devices manufactured in this type of technology 15 volts can be considered a "high" voltage, and without question 20-25 volts is certainly a "high" voltage.
Solutions which increase the device voltage are rendered relatively unacceptable if the processing employed to implement those solutions is at odds with the implementation of associated circuitry, thus requiring, for example, separate or off-chip devices. Thus, a solution to the high breakdown voltage problem should be compatible with the basic FET technology and thereby allow fabrication on the same chip, of relatively high speed, tightly packed circuits along with those circuits capable of tolerating relatively high voltages.
Typical FET devices include a semi-conductor substrate of one conductivity type with two diffused areas of another conductivity type separated by a channel. The channel may or may not, also contain an impurity implant, depending on whether the device is an enhancement or depletion mode device. An insulated gate overlies the channel and the voltage applied to the gate may be used to regulate the current flowing in the channel. In integrated circuit technology, devices (which in discrete logic technology are connected by a conductor) may actually share a common diffused region. One limiting factor in the voltage handling capability of FET devices is P-N junction breakdown caused by an increased electric field in the curved region near the junction edge. It is known in the prior art that such breakdown characteristics can be controlled (within a limited range), see for example, "Physics and Technology of Semiconductor Devices" by A. F. Grove, chapter 10, Wiley, N.Y., 1967. This limited control is effected by providing other gates, gate-like structures or shields which can be arranged to alter the local electric field.
However, a second problem which must be addressed in switching high voltages is the snap-back--sustaining voltage. An FET device exhibits this effect when the drain voltage is clamped relative to the source in response to excessive current loads on a drain junction which is biased near, but below avalanche breakdown. In a device which exhibits snap-back, the gate loses control and current can increase without any further increase in voltage. The prior art illustrates that relief or increase in the sustaining voltage can be obtained by increasing the effective channel length, or decreasing the channel width, but this control is limited.
A still further problem with switching high voltages in FET's is caused by charge being injected into the oxide, under the gate. More particularly, at sufficiently high fields, caused by excessive voltages, hot electrons are injected into the oxide insulator resulting in trapped charge which causes changes in device parameters.
It is therefore, one object of the present invention to provide a circuit capable of tolerating "high" voltages employing FETs. It is another object of the present invention to provide such a circuit in which the FET geometry and parameters do not require changes in the basic process so that the high voltage circuits of the invention can be incorporated in the same chip along with other conventional FET circuits. It is still a further object of the invention to provide such an FET circuit for switching high voltages which exhibits effective control over P-N junction breakdown, avoids sustaining voltages, and is not subject to hot electron injection. These and other objects of the invention will become apparent as this description proceeds.